1. Field of the Invention
The present invention relates to electrostatic charge measurement methods, focus adjustment methods, and scanning electron microscopes, and in particular, an electrostatic charge measurement method, a focus adjustment method, and a scanning electron microscope for measuring or observing automatically and with a high accuracy the dimension and the shape of the pattern formed on a semiconductor wafer.
2. Description of the Related Art
The greater scale of integration and miniaturization of semiconductor devices in recent years have resulted in formation of many diverse patterns on the wafer, and evaluation and measurement of dimensions and shapes of these patterns are becoming ever more important.
How fast the measurement points can be detected is critical for measuring a great number of measurement points automatically, at high speed, and with high accuracy, and for this purpose, it is necessary to focus on the pattern after shifting to the measurement point.
In order to measure the pattern dimension with high accuracy, an observing magnification is calculated from an accurate acceleration voltage in which the electrostatic charge voltage of the wafer is taken into consideration, to measure the pattern dimension. In an electron optical system, the conditions for focusing on the wafer are determined by the acceleration voltage of the electron beam and the height of the wafer.
The acceleration voltage of the electron beam is defined by an extraction voltage when the electron beam being extracted from an electron source, a retarding voltage applied to the wafer to decelerate the electron beam, and an electrostatic charge voltage of the wafer surface. A technique of controlling the application voltage to a sample according to the electrostatic charge voltage and the like of the wafer with the extraction voltage maintained constant to obtain a desired acceleration voltage regardless of the amount of electrostatic charge and the like is described in Japanese Patent Application Laid-Open No. 2001-52642, Japanese Patent Application Laid-Open No. 2001-236915 (corresponding to U.S. Pat. No. 6,521,891), and Japanese Patent Application Laid-Open No. 4-229541.
A technique of controlling the negative voltage (retarding voltage) to be applied to the sample according to the amount of electrostatic charge and the like is also referred to as a retarding focus, where the conditions for focus are changed by changing the retarding voltage while maintaining the extraction voltage of the electron beam constant, and the wafer electrostatic charge voltage of the measurement point can be calculated backwards from the retarding voltage of when focused on the wafer, the extraction voltage value, and the height of the wafer.
Japanese Patent Application Laid-Open No. 2006-19301 (corresponding to U.S. Pat. No. 6,946,656) discloses a technique of, in a scanning electron microscope equipped with an energy filter, gradually changing the application voltage to an energy filter while irradiating the sample with the electron beam, and measuring the electrostatic charge of the sample surface on the basis of the obtained graph waveform (hereinafter sometimes referred to as an S curve) indicating the transition of the detected quantity of electrons with respect to the change in application voltage to the energy filter.